Method of manufacturing CMOS integrated circuit

ABSTRACT

In a method of manufacturing a CMOS integrated circuit according to the present invention, a PSD step (step of forming P-type source/drain regions) is first carried out, and an NSD step (step of forming N-type source/drain regions) is thereafter carried out, in order to create a mixed structure of a silicide transistor and a non-silicide transistor. Thus, a step of depositing an oxide film on a substrate surface may be carried out only once, the oxide film can be removed by a single step of etching with hydrofluoric acid, and the operating characteristics of formed devices can be excellently maintained.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method of manufacturing a CMOSintegrated circuit, and more particularly, it relates to a method ofmanufacturing a CMOS integrated circuit mixedly provided with asilicified transistor and a non-silicified transistor.

2. Description of Related Art

A CMOS (Complementary Metal Oxide Semiconductor) integrated circuit hasadvantages such as small power consumption and a stable operation, andis widely applied to a VLSI (Very Large Scale Integrated Circuit). Inrecent years, a CMOS integrated circuit mixedly provided withtransistors of different types has also been implemented.

For example, a CMOS integrated circuit in which part of transistors aresilicide transistors and the other transistors are non-silicidetransistors is implemented. In this integrated circuit, the silicidetransistors exhibiting low gate, source and drain resistance values ofabout 15Ω can be utilized as transistors for high-speed operations,while the non-silicide transistors having excellent withstand voltagecharacteristics against external surge voltages, for example, can beutilized as input/output circuits to which high electrostatic withstandvoltages are required. Therefore, a semiconductor integrated circuitchip mixedly provided with the different types of silicide transistorsand non-silicide transistors can be used for various applications.

A conventional method of manufacturing a CMOS integrated circuit mixedlyprovided with silicide transistors and non-silicide transistorsgenerally performs first an NSD step of forming source and drain regionsfor N-type transistors after forming gate electrodes on the surface of asilicon substrate, then a PSD step of forming source and drain regionsfor P-type transistors, and thereafter a step of covering thenon-silicide transistors with oxide films and forming silicide films onthe gate electrodes, the source regions and the drain regions ofsilicified transistors.

In this case, As⁺ (arsenic) ions are implanted in the NDS step in orderto form the N-type source and drain regions, while the implanted As⁺ions may punch through the gate electrodes. In order to prevent this, anoxide film (TEOS film, for example) having a thickness of about 180 Åmust be deposited in advance of the NSD step, and the deposited TEOSfilm is removed with hydrofluoric acid after the NSD step.

When the transistors are selectively silicified, the non-silicifiedtransistors must be covered with protective oxide films (TEOS films, forexample). The silicifying step is carried out while depositing TEOSfilms having a thickness of about 500 Å, for example, on thenon-silicide transistors. Therefore, the TEOS films must be removed byetching with hydrofluoric acid after the silicifying step.

As hereinabove described, the conventional method inevitably includestwo steps of removing oxide films with hydrofluoric acid. In the stepsof removing the oxide films by etching with hydrofluoric acid, isolationoxide films (STI oxide films, for example) are excessively scraped offdue to overetching, to result in increase in borderless contact leakage.

The present invention has been proposed under the aforementionedcircumstances, and a main object of the present invention is to providea method of manufacturing a CMOS integrated circuit capable of ensuringa leakage margin for preventing increase in borderless contact leakage.

Another object of the present invention is to provide an improved methodof manufacturing a CMOS integrated circuit mixedly provided with asilicide transistor and a non-silicide transistor.

Further another object of the present invention is to provide a methodof manufacturing a CMOS integrated circuit reducing a hydrofluoric acidtreatment step for removing an oxide film.

SUMMARY OF THE INVENTION

In the method of manufacturing a CMOS integrated circuit according tothe present invention, a P well and an N well are formed, a PSD step offorming P-type source and drain regions in the N well is first carriedout, and an NSD step of forming N-type source and drain regions in the Pwell is thereafter carried out, whereby an oxide film is deposited onthe surface of a semiconductor substrate only once, and can be removedby a single step of etching with hydrofluoric acid. Therefore, theoperating characteristics of formed devices can be desiredly maintained.

Particularly in a case of manufacturing an integrated circuit mixedlyprovided with a silicide transistor and a non-silicide transistor,increase in borderless contact leakage is suppressed in each transistor,and a semiconductor integrated circuit having excellent characteristicscan be manufactured.

The foregoing and other elements, features, steps, characteristics andadvantages of the present invention will become more apparent from thefollowing detailed description of the preferred embodiments withreference to the attached drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a schematic sectional view showing a principal step in amethod of manufacturing a CMOS integrated circuit mixedly provided withsilicide transistors and non-silicide transistors according to anembodiment of the present invention.

FIG. 1B is a schematic sectional view showing a principal step in themethod of manufacturing a CMOS integrated circuit mixedly provided withsilicide transistors and non-silicide transistors according to theembodiment of the present invention.

FIG. 1C is a schematic sectional view showing a principal step in themethod of manufacturing a CMOS integrated circuit mixedly provided withsilicide transistors and non-silicide transistors according to theembodiment of the present invention.

FIG. 1D is a schematic sectional view showing a principal step in themethod of manufacturing a CMOS integrated circuit mixedly provided withsilicide transistors and non-silicide transistors according to theembodiment of the present invention.

FIG. 1E is a schematic sectional view showing a principal step in themethod of manufacturing a CMOS integrated circuit mixedly provided withsilicide transistors and non-silicide transistors according to theembodiment of the present invention.

FIG. 1F is a schematic sectional view showing a principal step in themethod of manufacturing a CMOS integrated circuit mixedly provided withsilicide transistors and non-silicide transistors according to theembodiment of the present invention.

FIG. 2 is a schematic sectional view showing one of the silicidetransistors included in the CMOS integrated circuit obtained through thesteps in the method of manufacturing a CMOS integrated circuit accordingto the embodiment of the present invention.

FIG. 3 illustrates the flow of the steps in the method of manufacturinga CMOS integrated circuit according to the embodiment of the presentinvention in comparison with the flow of conventional steps.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

FIGS. 1A to 1F are schematic sectional views showing partial steps in amethod of manufacturing a CMOS integrated circuit according to anembodiment of the present invention. More specifically, FIGS. 1A to 1Fare schematic sectional views showing in order principal steps in themethod of manufacturing a CMOS integrated circuit mixedly provided withsilicide transistors and non-silicide transistors.

FIG. 1A is a schematic sectional view showing four isolated transistorregions provided with gate electrodes and sidewalls respectively in themidway of the manufacturing process. Referring to FIG. 1A, a referencenumeral 11 denotes a P well and a reference numeral 12 denotes an Nwell, the P wells 11 and the N wells 12 of the so-called twin layerstructure are formed on a silicon wafer, and these wells 11 and 12 areisolated from one another by isolation oxide films 13 of an STI (ShallowTrench Isolation) structure or the like. Gate electrodes 15 are providedon the P wells 11 and the N wells 12 respectively through gate oxidefilms 14 made of SiO₂. Each gate electrode 15 is made of polysilicondoped with an N conductivity type impurity such as phosphorus orarsenic, for example. A pair of sidewalls 17 made of SiN, for example,are formed on both sides of the gate electrode 15 through thin oxidefilms 16.

N⁻ diffusion layers 18 are thinly formed on the surface layer regions ofthe P wells 11, to be bridged by the corresponding gate oxide films 14.On the other hand, P⁺ diffusion layers 18 are thinly formed on thesurface layer regions of the N wells 12, to be bridged by thecorresponding gate oxide films 14. The diffusion layers 18, alsoreferred to as extensions, are so provided as to prevent generation ofhot electrons or the like by forming source and drain diffusion regionslocated under the sidewalls 17 so as to have the so-called doublediffusion structures, as shown in FIG. 1F etc. described later.

The gate electrodes 15, the sidewalls 17 and the extensions 18 areformed through well-known steps. In other words, oxide films andpolysilicon films are deposited on the surfaces of the P wells 11 andthe N wells 12 respectively, and parts of the oxide films and thepolysilicon films other than the gate oxide films 14 and the gateelectrodes 15 are removed by photolithography. The gate electrodes 15are employed as masks to form the extensions 18 in a self-alignedmanner. The extensions 18 are individually formed on the P wells 11 andthe N wells 12 respectively. Thereafter an oxide film made of TEOS isthinly formed on the surface of the structure, and a film of SiN to formsidewalls is deposited and etched back to complete the sidewalls 17.Thus, the structure shown in FIG. 1A is obtained.

Referring to FIG. 1B, a PSD step is first carried out. In this step,source regions 19 and drain regions 20 of P⁺ diffusion layers are formedon the surface layer portions of the N wells 12. In order to carry outthis step, the upper surfaces of the P wells 11 are first covered withPSD (for forming P-type source/drain regions) resist films 21. Morespecifically, a PSD resist film 21 is applied to the entire surface of asilicon substrate, and selectively removed from the N wells 12 byphotolithography. Then, P⁺-type PSD ions, for example, are implanted inorder to form the diffusion layers 19 and 20. After termination of theion implantation, the resist films 21 remaining on the P wells 11 areremoved by ashing through O₂ plasma treatment, for example.

Then, an oxide film 22 made of TEOS is deposited on the entire uppersurface of the substrate, as shown in FIG. 1C. The thickness of theoxide film 22 is about 150 to 400 Å.

Then, an NSD step is carried out, as shown in FIG. 1D. In this step, theupper portions of the N wells 12 are selectively covered with resistfilms 23 (resist films for forming N-type source/drain regions;hereinafter referred to as NSD resist films) by photolithography. Then,As⁺ (arsenic) ions are implanted into the surface layer portions of theP wells 11, in order to form source regions 23 and drain regions 24 ofN⁺ diffusion layers. In this NSD step, the implanted As⁺ ions punchthrough polysilicon constituting the gate electrodes 15 unless the oxidefilm 22 is deposited. In order to prevent the As⁺ ions from punchingthrough the gate electrodes 15, therefore, the oxide film 22 is formedas a through preventing film. Thus, the source regions 23 and the drainregions 24 positioned by the gate electrodes 15 and the sidewalls 17 ina self-aligned manner can be formed on the surface layer portions of theP wells 11, as shown in FIG. 1D.

Then, a non-silicide transistor region is covered with a resist film 25(protective resist film 25) in order to selectively form silicidetransistors, as shown in FIG. 1E. This step is also carried out byphotolithography, and the protective resist film 25 is left only on theupper surface of the non-silicide transistor region. Thereafter theoxide film 22 covering the upper surface of the silicide transistorregion is removed by etching with hydrofluoric acid.

After the oxide film 22 is removed from the upper surface of thesilicide transistor region, cobalt is deposited on the entire surface ofthe substrate by sputtering and annealed at a temperature of about 800°C., thereby forming silicide films 26 and 27 of CoSi₂ on the surfacelayer portions of the gate electrodes 15 and the surface layer portionsof the source regions 23 and the drain regions 24 respectively, as shownin FIG. 1F. In this step, the substrate is first subjected topre-sputtering cleaning, and cobalt is thereafter deposited on theentire surface of the substrate by sputtering. The protective resistfilm 25 covering the non-silicide transistor region is removed by theannealing for forming the silicide films 26 and 27. The oxide film 22deposited on the upper surface of the non-silicide transistor regionpartially forms an interlayer film produced by CVD in a following step,and may not be removed.

This embodiment includes the aforementioned steps described withreference to FIGS. 1A to 1F, and the hydrofluoric acid etching step iscarried out only once when forming the mixed structure of the silicidetransistors and the non-silicide transistors. Therefore, such aninconvenience can be prevented that the STI oxide films 13 isolating thewells 11 and 12 from each other are excessively scraped off due tooveretching at the time of etching by hydrofluoric acid to increaseborderless contact leakage.

In other words, the NSD step is carried out after the PSD step accordingto this embodiment, reversely to the prior art, while the oxide film isdeposited on the surface of the substrate only once and removed by thesingle hydrofluoric acid etching step, whereby the operatingcharacteristics of formed devices can be desiredly maintained.

While the oxide film 22 is made of TEOS (the so-called TEOS film) in theaforementioned embodiment, the oxide film 22 is not necessarily be madeof TEOS but may be prepared from another material, so far as the oxidefilm 22 is removable with hydrofluoric acid and capable of preventingthe implanted As⁺ ions from punching through the gate electrodes 15.

FIG. 2 is a schematic sectional view showing one of the silicidetransistors included in the CMOS integrated circuit obtained through thesteps in the method of manufacturing a CMOS integrated circuit accordingto the embodiment of the present invention. The advantages or effects ofthe steps in the method of manufacturing a CMOS integrated circuitaccording to the present invention are described with reference to FIG.2.

The STI oxide film 13 functioning as isolation film is not scraped off(removed) by etching, and an end surface of the source region 23opposite to the gate electrode 15 is opposed to the corresponding STIoxide film 13. An edge of the drain region 24 opposite to the gateelectrode 15 is similarly sufficiently in contact with the correspondingSTI oxide film 13. Even if a contact 30 formed on the source region 23and the STI oxide film 13 are in borderless contact with each other (thecontact 30 is so provided as to come into contact with the STI oxidefilm 13), therefore, a leakage current can be prevented from flowingfrom the contact 30 into the substrate (well).

Assuming that two hydrofluoric acid etching steps are carried out inorder to manufacture the transistor, the STI oxide film 13 may bescraped off up to a degree shown by a broken line L1. If the STI oxidefilm 13 is scraped off by etching, electrons may transfer as shown bythick arrow in FIG. 2, to result in leakage between the contact 30 andthe substrate (well). In the method according to the embodiment of thepresent invention, however, a leakage margin is so provided as toprevent such leakage.

Further, the oxide film 22 removed by hydrofluoric acid is formed onlyonce, whereby no heat treatment is required for depositing the oxidefilm 22, and spreading of the extensions (diffusion layers) 18 issuppressed. Referring to FIG. 2, broken lines L2 denote spreading of theextensions 18 resulting from a large amount of heat treatment history.If the extensions 18 spread, the length of a channel region 31 locatedunder the gate electrode 15 is reduced, to result in such ashort-channel phenomenon that the source and drain regions 23 and 24 arelinked with each other due to punch through. According to the embodimentof the present invention, however, the short-channel characteristics ofthe transistor can be improved.

FIG. 3 illustrates the flow of the steps according to the embodiment ofthe present invention in comparison with the flow of conventional steps.Referring to FIG. 3, numerals “1A” to “1F” correspond to the steps shownin FIGS. 1A to 1F respectively.

The flow of the conventional steps shown in FIG. 3 includes two steps ofdepositing oxide films and two steps of removing the deposited oxidefilms.

In the flow of the steps according to the embodiment of the presentinvention, on the other hand, the oxide film is deposited only once andremoved only once.

The present invention is not limited to the aforementioned embodiment,but can be modified in various ways in the range of the scope of claimsfor patent.

For example, while the embodiment is described with reference to thetransistors each having the gate electrode sandwiched between the pairof sidewalls, the manufacturing method of the present invention is alsoapplicable to a transistor having a sidewall only on one side or atransistor having no sidewall.

While the present invention has been described in detail by way of theembodiments thereof, it should be understood that these embodiments aremerely illustrative of the technical principles of the present inventionbut not limitative of the invention. The spirit and scope of the presentinvention are to be limited only by the appended claims.

This application corresponds to Japanese Patent Application No.2007-173962 filed with the Japanese Patent Office on Jul. 2, 2007, thedisclosure of which is incorporated herein by reference.

1. A method of manufacturing a CMOS integrated circuit by formingisolated P and N wells on a surface layer region of a semiconductorsubstrate, forming gate electrodes on the respective wells, andthereafter sequentially carrying out: (1) a PSD step of forming P-typesource and drain regions on the N well; (2) an NSD step of formingN-type source and drain regions on the P well by depositing an oxidefilm on a surface of the substrate and selectively covering the N wellwith a resist film; (3) a step of selectively removing the resist film,thereafter selectively covering the N well and the P well for anon-silicide transistor not subjected to silicide formation with aresist film, and then removing the oxide film from the N well and the Pwell constituting a silicide transistor; and (4) forming a silicide onthe gate electrodes and the source and drain regions of the N well andthe P well from which the oxide film is removed.
 2. The method ofmanufacturing a CMOS integrated circuit according to claim 1, whereinthe NSD step includes a step of implanting As ions for forming theN-type source and drain regions.
 3. The method of manufacturing a CMOSintegrated circuit according to claim 2, employing hydrofluoric acid forselectively removing the oxide film.
 4. The method of manufacturing aCMOS integrated circuit according to claim 1, employing hydrofluoricacid for selectively removing the oxide film.